The present application relates to methods and systems for forming high performance, high uniformity, and high reliability low temperature polycrystalline thin film devices on glass substrates.
The following paragraphs contain some discussion, which is illuminated by the innovations disclosed in this application, and any discussion of actual or proposed or possible approaches in these paragraphs does not imply that those approaches are prior art.
Display devices, such as used in television and computer screens, are rapidly evolving into high quality flat-panel displays employing active-matrix driving technology. The latest displays technologies, such as liquid-crystal displays (LCD), organic light-emitting diodes (OLED), and electronic ink, all benefit from active-matrix driving. Active-matrix driving allows the realization of full colors and high resolution with significantly reduced cross talk. An essential key technology of active-matrix driving display is the fabrication of thin-film transistors (TFT) on a flat substrate, which is usually glass.
In conventional active-matrix displays, the TFTs are formed using amorphous silicon (a-Si). This is due to its low processing temperature and low manufacturing cost on large-area glass substrates. Recently polycrystalline silicon (poly-Si) is being deployed in the fabrication of high resolution liquid-crystal displays. Poly-Si also has the advantage that circuits can be integrated onto the glass substrate as well. Poly-Si also affords the possibility of larger aperture ratios on the pixel, thus increasing the light utilization efficiency and reducing power consumption for the display. For applications requiring large current, a-Si is not suitable and poly-Si has yet to be used.
To achieve the industrialized manufacture of a poly-Si TFT active-matrix display panels, a very high quality of poly-Si film is necessary. It needs to meet the requirements of the low temperature process, can be realized over large-area glass substrate, low manufacture cost, stable manufacture process, high performance, uniform characteristics, and high reliability of poly-Si TFT.
High temperature poly-Si technology can be used to achieve high performance TFT, but it cannot be applied to common glass substrates used in commercial display panels. Low temperature poly-Si (LTPS) must be used in such cases. There are three major LTPS technologies: (1) Solid-phase crystallization (SPC) by annealing at 600° C. for a long time; (2) excimer laser crystallization (ELC) or flash lamp annealing; and (3) metal induced crystallization (MIC) and its related variations. ELC produces the best results but is expensive. SPC is the least costly but takes a long time. None of these technologies can meet all the requirements of low cost and high performance mentioned above.
Common to all polycrystalline thin film materials is that the film's grains are essentially randomly distributed in size, in crystalline orientation and in shape. The grain boundaries are also usually detrimental to the formation of good TFTs. When this polycrystalline thin film is used as the active layer in TFT, the electrical characteristics depend on how many grains and grain boundaries are present in the active channel.
The common problem of all existing technologies is that they form many grains within the TFT active channel in a non-predictable pattern. The distribution of grains is random, making the electrical properties of the TFT somewhat non-uniform across the substrate. This wide distribution of electrical properties is detrimental to the performance of the display and leads to problems such as mura defects and non-uniform brightness.
The grains of a polycrystalline thin film transistor form a random network. This is true for any semiconductor material, such as silicon, germanium, silicon germanium alloy, three five compound semiconductors, as well as organic semiconductors. Conduction inside the grain is nearly the same as crystalline material, while conduction across the grain boundary is poorer and contributes to the overall loss of mobility and increased voltage threshold. Inside the active channel of a thin film transistor (TFT) made of such polycrystalline thin film, the grain structure is nearly a two dimensional random network. The randomness and consequential variable electrical conduction adversely effects display performance and picture quality.
As shown in FIG. 1a of a typical poly-Si structure, the low temperature poly-Si film 101 includes grains 102. There are obvious grain boundaries 103 between neighboring grains 102. Every grain 102 is sized from tens of nanometer to several microns in length and is considered as a single crystal. A lot of defects of dislocation, stack fault and dangling bond are distributed in the grain boundaries 103. Due to different preparation methods, the grains 102 inside of the low temperature poly-Si film 101 may be randomly distributed or in certain orientation.
As to conventional low temperature poly-Si film 101, there are serious defects in grain boundaries 103, as shown in FIG. 1b. The serious defects in grain boundaries 103 will introduce a high barrier potential 104. The barrier potential 104 perpendicular to (or the vertical component of the oblique barrier potential) the direction carrier 105 transportation will affect the initial state and ability of the carrier.
For the thin-film transistor fabricated on this low temperature poly-Si film 101, the threshold voltage and the field effect mobility are limited by the grain boundary barrier potential 104. The grain boundaries 103 distributed in the junction region also cause large leakage current when a high reverse gate voltage is applied in the TFT.
An effective way to improve the grain boundaries 103 (i.e. to reduce the grain boundary barrier potential 104) is to perform another post annealing on the low temperature poly-Si at 900° C.-1100° C. (refer to U.S. Pat. No. 6,225,197 and JP Patent 2001244198), or irradiate the poly-Si 101 by excimer laser or flash lamp (refer to US Publication 2005040402 and JP Patent 2004179195). After the post annealing or irradiation, the low temperature poly-Si film 101 is transformed into the post annealed poly-Si films 201, as shown in FIG. 2a. 
FIG. 2a is a schematic diagram of an annealed ELC low temperature poly-Si film 201 and corresponding barrier potential distribution as shown in FIG. 1b. Normally, the inside of grain 202 is basically the same as the original grain 102. Post annealing or irradiation can significantly ameliorate the grain boundaries 203. At the same time the grain boundary barrier potential 204 shown in FIG. 2b is considerably reduced. The mobility of carrier 205 is also greatly improved.
Applying the post annealed or irradiated poly-Si 201 film as the active layer of a TFT considerably improves the field-effect mobility and decreases the threshold voltage and the leakage current of the TFT over the conventional poly-Si TFT. However, there are still some limits to this technique. The temperature of the post annealing is around 900° C.-1100° C., which can not be applied to the common glass substrate used in a commercial display panel. Only quartz or some other high temperature-resistant material can be used as the substrate, which limits the size of the display and the cost of the panel.
If the low temperature poly-Si film 101 is post annealed with an excimer laser or a flash lamp, good mobility can be obtained. But this method is performed at a high cost. Moreover, it is well known that excimer laser annealing leads to non-uniform thin films due to laser beam non-uniformity. Furthermore, post annealing of the LTPS is more complicated than direct annealing of a-Si.
Another effective way to decrease the impact of the grain boundaries 103 (i.e. the grain boundary barrier potential 104) is to implant the intrinsic LIPS with low dose impurity, and adjusted it to a light p type or n type poly-Si as shown in FIG. 3a. This method is disclosed in “High-Performance Poly-Si TFTs With Multiple Selectively Doped Regions In The Active Layer” (Min-Cheol Lee, Juhn-Suk Yoo, Kee-Chan Park, Sang-Noon Jung, Min-Koo Han, and Hyun-Jae Kim, “High-Performance Poly-Si TFTs With Multiple Selectively Doped Regions In The Active Layer” 2000 Materials Research Society) and “A Novel Poly-Si TFTs with Selectively Doped Regions Fabricated by New Excimer Laser Annealing” (M. C. Lee, J. H. Jeon, I. H. Song, K. C. Park and M. K. Han, “A Novel Poly-Si TFTs with Selectively Doped Regions Fabricated by New Excimer Laser Annealing”, SID 01 Digest. p. 1246-1249).
The low temperature poly-Si film 301 contains distributed grains 302. The grain boundary 303 still possesses a higher grain boundary barrier potential 304 as shown in FIG. 3, though it is considerably reduced because of lightly doping the low temperature poly-Si film 301. The mobility of carrier 305 is also greatly improved because of the reduced barrier potential 304.
The observed reduction is achieved by light dosage ion implantation lowering the grain boundary potential 304 by implanting impurities into the grains 302. For example, if the ions B+ at dose of 5×1012 atoms/cm2 are implanted into the low temperature poly-Si 101, the threshold voltage can be lowered by several volts. However, with the increasing of the doping dose, the leakage current will increase. Implantation can adjust the threshold voltage in a certain range, but it contributes little to the field effect mobility and to the reduction of the leakage current. Thus, it is only a partial solution.
Furnace annealing is a commonly used method for obtaining low temperature poly-Si below 600° C. It is applied in the case of solid phase crystallization (SPC) or metal induced crystallization (MIC). However, SPC and MIC cannot achieve TFT with a high performance as those obtained with ELA post annealing or high temperature post annealed poly-Si. In the present technique, we make use of furnace annealing of low temperature poly-Si to achieve TFT with high performance, high uniformity, and high stability. The quality of this type of LTPS TFT can be as good as the LTPS TFT obtained by high temperature annealing or ELA annealing. The new technique can also be applied to ELA or flash lamp annealed TFT to improve its uniformity as well.
The grains of a polycrystalline thin film transistor form a random network in conventional TFTs made from any semiconductor material, such as silicon, germanium, silicon germanium alloy, three five compound semiconductors, as well as organic semiconductors. Conduction across grain boundaries is poorer than within the crystalline material and contributes to the overall loss of mobility and increased voltage threshold. Inside the active channel of a thin film transistor (TFT) made of such polycrystalline thin film, the grain structure is nearly a two dimensional random network.
In the present invention, we disclose a method to improve the properties of TFT made with all of the above techniques. Important properties such as threshold voltage, on-off ratio, device mobility, device uniformity across the substrate and sub-threshold slope, can all be improved using the present invention. The improvement can be achieved at low cost, thus making inexpensive, high performance LTPS TFT a reality.